The invention relates to an integrated circuit having a resistively switching memory cell, in one embodiment a Phase Change Random Access Memory (“PCRAM”), and a memory device including such memory cells. The invention further relates to a method of operating an integrated circuit having a resistively switching memory cell and a method of operating a resistively switching memory device. The invention further relates to a method of manufacturing a memory device.
In the case of conventional memory devices, in particular conventional semiconductor memory devices, one differentiates between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory—in particular PROMs, EPROMs, EEPROMs, flash memories, etc.), and RAM devices (RAM=Random Access Memory—in particular e.g., DRAMs and SRAMs).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later. In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g., of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element.
Furthermore, “resistive” or “resistively switching” memory devices have also become known recently, e.g., Phase Change Random Access Memories (“PCRAMs”), Conductive Bridging Random Access Memories (“CBRAMs”), Magnetoresistive Random Access Memories (“MRAM”) etc.
In the case of “resistive” or “resistively switching” memory devices, an “active” or “switching active” material—which is, for instance, positioned between two appropriate electrodes—is placed, by appropriate switching processes, in a more or less conductive state (wherein e.g., the more conductive state corresponds to a stored logic “One”, and the less conductive state to a stored logic “Zero”, or vice versa).
In the case of Phase Change Random Access Memories (PCRAMs), for instance, an appropriate chalcogenide or chalcogenide compound material may be used as a “switching active” material (e.g., a Ge—Sb—Te (“GST”) or an Ag—In—Sb—Te compound material, etc.). The chalcogenide compound material is adapted to be placed in an amorphous, i.e. a relatively weakly conductive, or a crystalline, i.e. a relatively strongly conductive state by appropriate switching processes (wherein e.g., the relatively strongly conductive state may correspond to a stored logic “One”, and the relatively weakly conductive state may correspond to a stored logic “Zero”, or vice versa). Alternatively, a chalcogenide free material may be used.
In the case of the above Conductive Bridging Random Access Memories (CBRAMs), the storing of data is performed by use of a switching mechanism based on the statistical bridging of multiple metal rich precipitates in the “switching active” material. Upon application of a write pulse (positive pulse) to two respective electrodes in contact with the “switching active” material, the precipitates grow in density until they eventually touch each other, forming a conductive bridge through the “switching active” material, which results in a high-conductive state of the respective CBRAM memory cell. By applying a negative pulse to the respective electrodes, this process can be reversed, hence switching the CBRAM memory cell back in its low-conductive state.
Correspondingly similar as is the case for the above PCRAMs, for CBRAM memory cells an appropriate chalcogenide or chalcogenide compound (for instance GeSe, GeS, AgSe, CuS, etc.), or a chalcogenide free material may be used as “switching active” material.
In the case of PCRAMs, in order to achieve, with a corresponding PCRAM memory cell, a change from the above-mentioned amorphous, i.e. a relatively weakly conductive state of the switching active material, to the above-mentioned crystalline, i.e. a relatively strongly conductive state of the switching active material, an appropriate relatively high heating current pulse has to be applied to the electrodes, the heating current pulse resulting in that the switching active material is heated beyond the crystallization temperature and crystallizes (“writing process”).
Vice versa, a change of state of the switching active material from the crystalline, i.e. a relatively strongly conductive state, to the amorphous, i.e. a relatively weakly conductive state, may, for instance, be achieved in that—again by an appropriate (relatively high) heating current pulse—the switching active material is heated beyond the melting temperature and is subsequently “quenched” to an amorphous state by quick cooling (“erasing process”).
Typically, the above erase or write heating current pulses are provided via respective source lines and bit lines, and respective FET or bipolar access transistors associated with the respective memory cells, and controlled via respective word lines.
To be cost competitive, a small cell size is desired, requiring a high density of the memory cell array. With planar array transistors, or with a transistor where the source/drain contacts are lying in the same horizontal plane (for example: FinFET), the cell size is limited to 6F2 for geometrical reasons.
In order to go below 6F2 for a 1T1R cell, a transistor with vertical current flow is desired, featuring a diffused buried ground plate electrode. However, a diffused plate does not have an unlimited conductance. At the array edges, a ground plate connection can be established via implanted well connections. However, such a wiring inside an array is consuming much area.
Thus, there still exists a need for a memory device including volatile memory cells of a small cell size and compact arrangement.
For these and other reasons, there is a need for the present invention.